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Z80C30/Z85C30
CMOS SCC Serial Communications Controller
Product Specification
PS011701-0701
ZiLOG Worldwide Headquarters * 910 E. Hamilton Avenue * Campbell, CA 95008 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com
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Document Disclaimer
(c) 2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
iii
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Other Features for Z85C30 Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Z85C30/Z80C30 Common Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Z80C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Interface Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30/Z80C30 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30/Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 Read/Write Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30/Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 19 40 40 40 41 48 51 55 55 55 57 57 57 57 59 59 83 83 84 84
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Table of Contents
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
iv
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
v
List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. SCC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Z85C30 and Z80C30 DIP Pin Assignments . . . . . . . . . . . . . . . . . . 13 Z85C30 and Z80C30 PLCC Pin Assignments . . . . . . . . . . . . . . . . . 14 Z85C30 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Z80C30 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SCC Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SCC Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SCC Interrupt Priority Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Some SCC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Detecting 5- or 7-Bit Synchronous Characters . . . . . . . . . . . . . . . . 28 An SDLC Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Encoding Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SDLC Frame Status FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SDLC Byte Counting Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Write Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Write Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Write Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Write Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Read Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Read Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . 51 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . 54 Standard Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Open-Drain Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Z85C30 Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 60 Z85C30 Interrupt Acknowledge Timing Diagram . . . . . . . . . . . . . . . 61 Z85C30 Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Z85C30 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Z85C30 General Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Z85C30 System Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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List of Figures
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
vi
Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
Z80C30 Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . Z80C30 Interrupt Acknowledge Timing Diagram. . . . . . . . . . . . . . . Z80C30 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30 General Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30 System Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 40-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-Pin PLCC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
73 74 74 79 82 83 84
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List of Figures
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
vii
List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. SCC Read Register Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCC Write Register Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30/Z85C30 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 General Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 System Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z85C30 Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30 Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30 General Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30 System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z80C30/Z85C30 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 20 20 57 58 62 68 71 72 75 80 83 85
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List of Tables
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
viii
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List of Tables
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
1
Overview
* * * * *
Z85C30: Optimized for Non-Multiplexed Bus Microprocessors. Z80C30: Optimized for Multiplexed Bus Microprocessors Pin Compatible to NMOS Versions Two Independent, 0 to 4.1 Mbit/Second, Full-Duplex Channels. Each channel with Separate Crystal Oscillator, Baud Rate Generator, and Digital Phase-Locked Loop (DPLL) for Clock Recovery. Multi-Protocol Operation under Program Control; Programmable for NRZ, NRZI, or FM Data Encoding. Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two Stop Bits Per Character, Programmable Clock Factor, Break Detection and Generation; Parity, Overrun, and Framing Error Detection. Synchronous Mode with Internal or External Character Synchronization on One or Two Synchronous Characters and CRC Generation and Checking with CRC-16 or CRC-CCITT Preset to either 1s or 0s. SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero Insertion and Deletion, I-Field Residue Handling, Abort Generation and Detection, CRC Generation and Checking, and SDLC Loop. Software Interrupt Acknowledge Feature (not available with NMOS) Local Loopback and Auto Echo Modes Supports T1 Digital Trunk Enhanced DMA Support (not available with NMOS) 10 x 19-Bit Status FIFO 14-Bit Byte Counter
*
*
* * * *
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Overview
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
2
*
Speeds: - Z85C3O-8.5, 10, 16.384 MHz - Z80C3O-8, 10 MHz
Other Features for Z85C30 Only
Some of the features listed below are available by default. Some of them (features with *) are disabled on default to maintain compatibility with the existing SCC design, and "program to enable through WR7".
* *
New programmable WR7' (write register 7 prime) to enable new features Improvements to support SDLC mode of synchronous communication - Improve functionality to ease sending back-to-back frames - Automatic SDLC opening Flag transmission* - Automatic Tx Underrun/EOM Latch reset in SDLC mode* - Automatic RTS deactivation* - TxD pin forced High in SDLC NRZI mode after closing flag* - Complete CRC reception* - Improved response to Abort sequence in status FIFO - Automatic Tx CRC generator preset/reset - Extended read for write registers* - Write data set-up timing improvement Improved AC timing - Three to 3.6 PCLK access recovery time. - Programmable DTR/REQ timing*
*
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Overview
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
3
- -
Write data to falling edge of WR set-up time requirement is now eliminated Reduced INT timing
*
Other features include. - Extended read function to read back the written value to the write registers.* - Latching RRO during read - RRO, bit D7 and RR10, bit D6 now has reset default value.
Overview
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
4
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Overview
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
5
General Description
The ZiLOG Z80C30/Z85C30 Serial Communications Controller (SCC), is a pin and software compatible CMOS member of the SCC family introduced by ZiLOG in 1981. It is a dual channel, multi-protocol data communications peripheral that easily interfaces to CPU's with either multiplexed or non-multiplexed address/ data buses. The advanced CMOS process offers lower power consumption, higher performance, and superior noise immunity. The programming flexibility of the internal registers allows the SCC to be configured to satisfy a wide variety of serial communications applications. Figure 1 illustrates a block diagram of the SCC. The many on-chip features such as Baud Rate Generators (BRG), Digital Phase Locked Loops (DPLL), and crystal oscillators reduce the need for external logic. Additional features include a 10 x 19-bit status FIFO and 14-bit byte counter to support high speed SDLC transfers using DMA controllers. The SCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (cassette, diskette, tape drives, etc.). The device generates and checks CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The SCC also contains facilities for modem controls in both channels. In applications where these controls are not needed, the modem controls can be used for general-purpose I/O. The daisy-chain interrupt hierarchy is also supported.
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General Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
6
Transmit Logic Transmit MUX Transmit Buffer
Data Encoding & CRC Generation
TxDA
Channel A
Exploded View Receive and Transmit Clock Multiplexer Digital Baud Rate Phase-Locked Generator Loop Crystal Oscillator Amplifier TRxCA RTxCA
CTSA DCDA Modem/Control Logic SYNCA RTSA DTRA/REQA
Receive Logic
Rec. Status Rec. Status FIFO 3 Byte FIFO 3 Byte
Receive MUX
RxDA
SDLC Frame Status FIFO 10 X 19
CRC Checker Data Decode & Sync Character Detection
Interrupt Control Logic Databus Control
Channel A Register
Channel A
CPU & DMA Bus Interface INT INTACK IEI IEO
Interrupt Control
Interrupt Control Logic
Channel B Register
Channel B
Figure 1. SCC Block Diagram
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General Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
7
Pin Descriptions
Z85C30/Z80C30 Common Pin Functions
The following section describes the pin functions common to the Z85C30 and the Z80C30. Figures 2 and 3 detail the respective pin assignments and Figures 4 and 5 designate the pin functions. CTSA, CTSB Clear To Send (inputs, active Low). If these pins are programmed for Auto Enable, a Low on the inputs enables the respective transmitters. If not programmed as Auto Enable, they may be used as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate slow rise-time inputs.The SCC detects pulses on these inputs and can interrupt the CPU on both logic level transitions. DCDA, DCDB Data Carrier Detect (inputs, active Low). These pins function as receiver enables if they are programmed for Auto Enable. Otherwise, these pins are used as general-purpose input pins. Both pins are Schmitt-trigger buffered to accommodate slow rise-time signals. The SCC detects pulses on these pins and can interrupt the CPU on both logic level transitions. DTR/REQA, DTR/REQB Data Terminal Ready/Request (outputs, active Low). These outputs follow the state programmed into the DTR bit. They can also be used as general-purpose outputs or as Request lines for a DMA controller.
General Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
8
IEI Interrupt Enable In (input, active High). IEI is used with IEO to form an interrupt daisy-chain when there is more than one interrupt driven device. A high IEI indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. IEO Interrupt Enable Out (output, active High). IEO is High only if IEI is High and the CPU is not servicing the SCC interrupt or the SCC is not requesting an interrupt (interrupt Acknowledge cycle only). IEO is connected to the next lower priority device's IEI input and thus inhibits interrupts from lower priority devices. INT Interrupt Request (output, open-drain, active Low). This signal activates when the SCC requests an interrupt. INTACK Interrupt Acknowledge (input, active Low). This signal indicates an active Interrupt Acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When RD or DS becomes active, the SCC places an interrupt vector on the data bus (if IEI is High). INTACK is latched by the rising edge of PCLK. PCLK Clock (input). This is the master SCC clock used to synchronize internal signals. PCLK is a TTL level signal. PCLK is not required to have any phase relationship with the master system clock.
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General Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
9
RxDA, RxDB Receive Data (inputs, active High). These signals receive serial data at standard TTL levels. RTXCA, RTXCB Receive/Transmit Clocks (inputs, active Low). These pins can be programmed in several different operating modes. In each channel, RTxC may supply the receive clock, the transmit clock, the clock for the Baud Rate Generator, or the clock for the Digital Phase-Locked Loop. These pins can also be programmed for use with the respective SYNC pins as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in Asynchronous modes. RTSA, RTSB Request To Send (outputs, active Low). When the Request To Send (RTS) bit in Write Register 5 (Figure 9) sets, the IRTS signal goes Low. When the RTS bit is reset in the Asynchronous mode and Auto Enable is on, the signal goes High after the transmitter is empty. In Synchronous mode it strictly follows the state of the RTS bit. Both pins can be used as general-purpose outputs. SYNCA, SYNCB Synchronization (inputs or outputs, active Low). These pins function as inputs, outputs, or part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal oscillator option not selected), these pins are inputs similar to CTS and DCD. In this mode, transitions on these lines affect the state of the Synchronous/Hunt status bits in Read Register 0 (Figure 8) but have no other function.
General Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
10
In External Synchronization mode with the crystal oscillator not selected, these lines also act as inputs. In this mode, SYNC must be driven Low for two receive clock cycles after the last bit in the synchronous character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of SYNC. In the Internal Synchronization mode (Monosync and Bisync) with the crystal oscillator not selected, these pins act as outputs and are active only during the part of the receive clock cycle in which synchronous characters are recognized This synchronous condition is not latched. These outputs are active each time a synchronization pattern is recognized (regardless of character boundaries). In SDLC mode, these pins act as outputs and are valid on receipt of a flag. TxDA, TxDB Transmit Data (outputs, active High). These output signals transmit serial data at standard TTL levels. TRXCA, TRXCB Transmit/Receive Clocks (inputs or outputs, active low). These pins can be programmed in several different operating modes. TRxC may supply the receive clock or the transmit clock in the input mode or supply the output of the Digital Phase-locked loop, the crystal oscillator, the Baud Rate Generator, or the transmit clock in the output mode. W/REQA, W/REQB Wait/Request (outputs, open-drain when programmed for a Wait function, driven High or low when programmed for a Request function). These dual-purpose outputs may be programmed as
PS011701-0701
General Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
11
Request lines for a DMA controller or as Wait lines to synchronize the CPU to the SCC data rate. The reset state is Wait.
Z85C30
A/B Channel A/Channel B (input). This signal selects the channel in which the read or write operation occurs. CE Chip Enable (input, active Low). This signal selects the SCC for a read or write operation. D7-D0 Data Bus (bidirectional, tri-state). These lines carry data and command to and from the SCC. D/C Data/Control Select (input). This signal defines the type of information transferred to or from the SCC. A High indicates a data transfer; a Low indicates a command. RD Read (input, active Low). This signal indicates a read operation and when the SCC is selected, enables the SCC's bus drivers. During the Interrupt Acknowledge cycle, this signal gates the interrupt vector onto the bus if the SCC is the highest priority device requesting an interrupt.
General Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
12
WR Write (input, active Low). When the SCC is selected, this signal indicates a write operation. The coincidence of IAD and WR is interpreted as a reset.
Z80C30
AD7-AD0 Address/Data Bus (bidirectional, active High, Tri-state). These multiplexed lines carry register addresses to the SCC as well as data or control information. AS Address Strobe (input, active Low). Addresses on AD7-AD0 are latched by the rising edge of this signal. CS0 Chip Select 0 (input, active Low). This signal is latched concurrently with the addresses on AD7-AD0 and must be active for the intended bus transaction to occur. CS1 Chip Select 1 (input, active High). This second select signal must also be active before the intended bus transaction can occur. CS1 must remain active throughout the transaction.
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General Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
13
DS Data strobe (input, active Low). This signal provides timing for the transfer of data into and out of the SCC. If AS and DS coincide, this confluence is interpreted as a reset. R/W Read/Write (input). This signal specifies whether the operation to be performed is a read or a write.
D1 D3 D5 D7 INT IEO IEI INTACK +5v W/REQA SYNCA RTxCA RxDA TRxCA TxDA DTR/REQA RTSA CTSA DCDA PCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 D0 D2 D4 D6 RD WR A/B CE D/C GND W/REQB SYNCB RTxCB RxDB TRxCB TxDB DTR/REQB RTSB CTSB DCDB AD1 AD3 AD5 AD7 INT IEO IEI INTACK +5v W/REQA SYNCA RTxCA RxDA TRxCA TxDA DTR/REQA RTSA CTSA DCDA PCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 AD0 AD2 AD4 AD6 DS AS R/W CS0 CS1 GND W/REQB SYNCB RTxCB RxDB TRxCB TxDB DTR/REQB RTSB CTSB DCDB
Z85C30
31 30 29 28 27 26 25 24 23 22 21
Z80C30
31 30 29 28 27 26 25 24 23 22 21
Figure 2. Z85C30 and Z80C30 DIP Pin Assignments
General Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
14
INT AD7 AD5
AD3
AD1
AD0
AD2
AD4
AD6
WR
INT D7 D5
RD
DS
6 IEO IEI INTACK +5V W/REQA SYNCA RTxCA RxDA TRxCA TxDA NC 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35
6 A/B CE D/C NC IEO IEI INTACK +5V 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35
AS
D3
D1
D0
D2
D4
D6
R/W CS0 CS1 NC GND W/REQB SYNCB RTxCB RxDB TRxCB TxDB
Z85C30
34 33 32 31 30
W/REQA GND W/REQB SYNCA SYNCB RTxCB RxDB TRxCB TxDB RTxCA RxDA TRxCA TxDA NC
Z80C30
34 33 32 31 30
29 18 19 20 21 22 23 24 25 26 27 28 DCDA DCDB NC DTR/REQA RTSA CTSA CTSB RTSB DTR/REQB PCLD NC
29 18 19 20 21 22 23 24 25 26 27 28 DCDA NC DTR/REQA RTSA DCDB CTSA CTSB RTSB DTR/REQB PCLK NC
Figure 3. Z85C30 and Z80C30 PLCC Pin Assignments
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General Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
15
D7 D6 D5 Data Bus D4 D3 D2 D1 D0 Bus Timing and Reset RD WR A/B Control CE D/C INT Interrupt INTACK IEI IEO
TxDA RxDA TRxCA RTxCA SYNCA W/REQA DTR/REQA RTSA CTSA
Serial Data Channel Clocks CH-A
Channel Controls for Modem, DMA and Other
Z85C30
DCDA TxDB RxDB TRxCB RTxCB SYNCB Serial Data Channel Clocks CH-B Channel Controls for Modem, DMA and Other
W/REQB DTR/REQB RTSB CTSB DCDB
Figure 4. Z85C30 Pin Functions
General Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
16
AD7 AD6 AD5 Data Bus AD4 AD3 AD2 AD1 AD0 Bus Timing and Reset AS DS R/W Control CS1 CS0 INT Interrupt INTACK IEI IEO
TxDA RxDA TRxCA RTxCA SYNCA W/REQA DTR/REQA RTSA CTSA
Serial Data Channel Clocks CH-A
Channel Controls for Modem, DMA and Other
Z80C30
DCDA TxDB RxDB TRxCB RTxCB SYNCB Serial Data Channel Clocks CH-B Channel Controls for Modem, DMA and Other
W/REQB DTR/REQB RTSB CTSB DCDB
Figure 5. Z80C30 Pin Functions
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General Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
17
Functional Description
The architecture of the SCC is described from two points of view:
* *
As a data communications device which transmits and receives data in a wide variety of protocols; As a microprocessor peripheral in which the SCC offers valuable features such as vectored interrupts and DMA support.
The SCC's peripheral and data communication are described in the following sections. Figure 1 on page 6 illustrates the SCC block diagram. Figures 6 and 7 show the details of the communications between the receive and transmit logic to the system bus. The features and data path for each of the SCC's A and B channels is identical.
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
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Internal Data Bus To Other Channel Internal TXD WR7 SYNC Register SYNC WR6 Register Final TX MUX TXD WRB TX Buffer 1 Byte
20-Bit TX Shift Register
Sync Sync Zero Insert (5 Bits) SDLC Transmit MUX & 2-Bit Delay NRZ Encode
Transmit Clock CRC-Gen
From Receiver
Figure 6. SCC Transmit Data Path
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
19
CPU/I/O
I/O Data buffer Internal Data Bus
Upper Byte (WR13) Time Constant
Lower Byte (WR12) Time Constant
Status FIFO 10 X 19 Frame
Rec. Error FIFO 3 Byte Deep
Rec. Error FIFO 3 Byte Deep
BRG Input
16-Bit Down Counter
DIV 2
BRG Output
14-Bit Counter Hunt Mode (BISYNC) DPLL IN
Rec. Error Logic
DPLL Internal TXD
DPLL OUT
SYNC Register & Zero Delete
3-Bit
Receive Shift Register
RXD
1-Bit
MUX
NRZI Decode
MUX SDLC-CRC
CRC Delay Register (8 bits) CRC Checker
SYNC CRC CRC Result
To Transmit Section
Figure 7. SCC Receive Data Path
I/O Interface Capabilities
System communication to and from the SCC is performed through the SCC's register set. There are sixteen write registers and eight read registers. Tables 1 and 2 list all SCC registers and provide a brief description of their functions.
Functional Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
20
Throughout this document. the write and read registers are referenced with the following notation "WR" for Write Register and "RR" for Read Register. For example: WR4A RR3 Write Register 4 for channel A Read Register 3 for either/both channels
Table 1. SCC Read Register Functions Register RR0 RR1 RR2 RR3 RR8 RR10 RR12 RR13 RR15 Function Transmit/Receive buffer status and External status Special Receive Condition status Modified interrupt vector (Channel B only) Unmodified interrupt vector (Channel A only) Interrupt Pending bits (Channel A only) Receive Buffer Miscellaneous status Lower byte of Baud Rate Generator time constant Upper byte of Baud Rate Generator time constant External/Status interrupt information
Table 2. SCC Write Register Functions Register WR0 WR1 Function CRC initialize, initialization commands for the various modes, register pointers Transmit/Receive interrupt and data transfer mode definition
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
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Table 2. SCC Write Register Functions (continued) Register WR2 WR3 WR4 WR5 WR6 WR7 WR7* WR8 WR9 WR10 WR11 WR12 WR13 WR14 WR15 Function Interrupt vector (accessed through either channel) Receive parameters and control Transmit/Receive miscellaneous parameters and modes Transmit parameters and controls Sync characters or SDLC address field
Sync character or SDLC flag
Extended Feature and FIFO Control (WR7 Prime)
85C30 Only
Transmit buffer Master interrupt control and reset (accessed through either channel) Miscellaneous transmitter/receiver control bits Clock mode control Lower byte of Baud Rate Generator time constant Upper byte of Baud Rate Generator time constant Miscellaneous control bits External/Status interrupt control
There are three methods to move data into and out of the SCC:
* * *
Polling Interrupt (vectored and non-vectored) Block Transfer. The Block Transfer mode can be implemented under CPU or DMA control.
Functional Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
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Polling When polling, all interrupts are disabled. Three status registers in the SCC are automatically updated whenever any function is performed. For example, End-Of-Frame in SDLC mode sets a bit in one of these status registers. The purpose of polling is for the CPU to periodically read a status register until the register contents indicate the need for data to be transferred. Only one register is read. Depending on its contents, the CPU either writes data, reads data, or continues. Two bits in the register indicate the need for data transfer. An alternative is a poll of the Interrupt Pending register to determine the source of an interrupt. The status for both channels resides in one register. Interrupts The SCC's interrupt structure supports vectored and nested interrupts. Nested interrupts are supported with the interrupt acknowledge feature (INTACK pin) of the SCC. This allows the CPU to recognize the occurrence of an interrupt, and re-enable higher priority interrupts Because an INTACK cycle releases the INT pin from the active state, a higher priority SCC interrupt or another higher priority device can interrupt the CPU. When an SCC responds to an Interrupt Acknowledge signal (INTACK) from the CPU, an interrupt vector can be placed on the data bus. This vector is written in WR2 and may be read in RR2. To speed interrupt response time, the SCC can modify three bits in this vector to indicate status. If the vector is read in Channel A, status is never included. If the vector is read in Channel B, status is always included. Each of the six sources of interrupts in the SCC (Transmit, Receive, and External/Status interrupts in both channels) has three bits associated with the interrupt source. Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). Operation
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
23
of the IE bit is straight forward. If the IE bit is set for a given interrupt source, then that source can request interrupts. The exception is when the MIE (Master Interrupt Enable) bit in WR9 is reset and no interrupts can be requested. The IE bits are write only. The other two bits are related to the interrupt priority chain (Figure 8). As a microprocessor peripheral, the SCC may request an interrupt only when no higher priority device is requesting one, that is, when IEI is High. If the device in question requests an interrupt, it pulls down INT. The CPU responds with INTACK, and the interrupting device places the vector on the data bus.
+5 V
Peripheral IEI D7-D0 INT INTACK IEO
Peripheral IEI D7-D0 INT INTACK IEO
Peripheral IEI D7-D0 INT INTACK +5 V
D7-D0 INT INTACK
Figure 8. SCC Interrupt Priority Schedule
The SCC can also execute an interrupt acknowledge cycle through software. In some CPU environments, it is difficult to create the INTACK signal with the necessary timing to acknowledge interrupts and allow the nesting of interrupts. In these cases, the INTACK signal can be created with a software command to the SCC. In the SCC, the Interrupt Pending (IP) bit signals a need for interrupt servicing. When an IP bit is 1 and the IEI input is High, the INT output is pulled Low, requesting an interrupt. In the SCC, if the IE bit is not set by enabling interrupts, then the IP for that source is never set. The IP bits are readable in RR3A.
Functional Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
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The IUS bits signal that an interrupt request is being serviced. If an IUS is set, all interrupt sources of lower priority in the SCC and external to the SCC are prevented from requesting interrupts. The internal interrupt sources are inhibited by the state of the internal daisy chain, while lower priority devices are inhibited by the IEO output of the SCC being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an Interrupt Acknowledge cycle if there are no higher priority devices requesting interrupts. There are three types of interrupts: Transmit, Receive, and External/Status. Each interrupt type is enabled under program control with Channel A having higher priority than Channel B, and with Receiver, Transmit, and External/Status interrupts prioritized in that order within each channel. When enabled, the receiver interrupts the CPU in one of three ways.
* * *
Interrupt on First Receive Character or Special Receive Condition Interrupt on All Receive Characters or Special Receive Conditions Interrupt on Special Receive Conditions Only
Interrupt on First Character or Special Condition and Interrupt on Special Condition Only are typically used with the Block Transfer mode. A special Receive Condition is one of the following. receiver overrun, framing error in Asynchronous mode, end-of-frame in SDLC mode and, optionally, a parity error. The Special Receive Condition interrupt is different from an ordinary receive character available interrupt only by the status placed in the vector during the Interrupt Acknowledge cycle. In Interrupt on First Receive Character, an interrupt occurs from Special Receive Conditions anytime after the first receive character interrupt. The main function of the External/Status interrupt is to monitor the signal transitions of the CTS, DCD, and SYNC pins, however, an External/Status interrupt is also caused by a Transmit Underrun
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
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condition; a zero count in the Baud Rate Generator; by the detection of a Break (Asynchronous mode), Abort (SDLC mode) or EOP (SDLC Loop mode) sequence in the data stream. The interrupt caused by the Abort or EOP has a special feature allowing the SCC to interrupt when the Abort or EOP sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the Abort condition in external logic in SDLC mode. In SDLC Loop mode, this feature allows secondary stations to recognize the primary station regaining control of the loop during a poll sequence. Software Interrupt Acknowledge On the CMOS version of the SCC, the SCC interrupt acknowledge cycle can be initiated through software. If Write Register 9 (WR9) bit D5 is set, Read Register 2 (RR2) results in an interrupt acknowledge cycle to be executed internally. Like a hardware INTACK cycle, a software acknowledge causes the INT pin to return High, the IEO pin to go low and set the IUS latch for the highest priority interrupt pending. Similar to using the hardware INTACK signal, a software acknowledge cycle requires that a Reset Highest IUS command be issued in the interrupt service routine. Whenever an interrupt acknowledge cycle is used, hardware or software, a reset highest IUS command is required. If RR2 is read from channel A, the unmodified vector is returned. If RR2 is read from channel B, then the vector is modified to indicate the source of the interrupt. The Vector Includes Status (VIS) and No Vector (NV) bits in WR9 are ignored when bit 05 is set to 1. When the INTACK and IEI pins are not being used, they should be pulled up to VCC through a resistor (10 K ohm typical).
Functional Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
26
CPU/DMA Block Transfer. The SCC provides a Block Transfer mode to accommodate CPU block transfer functions and OMA controllers. The Block Transfer mode uses the WAIT/REOUEST output in conjunction with the Wait/Request bits in WR1. The WAIT/REOUEST output can be defined under software control as a WAIT line in the CPU Block Transfer mode or as a REQUEST line in the DMA Block Transfer mode. To a DMA controller, the SCC REQUEST output indicates that the SCC is ready to transfer data to or from memory To the CPU, the WAIT line indicates that the ESCC is not ready to transfer data, thereby requesting that the CPU extend the I/O cycle. The DTR/ REQUEST line allows full-duplex operation under DMA control. SCC Data Communications Capabilities The SCC provides two independent full-duplex programmable channels for use in any common asynchronous or synchronous data communication protocols (Figure 9). Each of the data communication channels has identical features and capabilities.
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
27
Start
Parity Stop
Marking Line
Data
Data
Data
Marking Line
Asynchronous
SYNC
Data
Data
CRC1
CRC2
Monosync
CRC1 CRC2
SYNC
SYNC Signal
Data
Data
Bisync
CRC2
Data
Data
CRC1
External Sync
Flag
Address
Information
Information
CRC1
CRC2
Flag
SDLC/HDLC/X.25
Figure 9. Some SCC Protocols
Asynchronous Modes Send and Receive is accomplished independently on each channel with five to eight bits per character, plus optional even or odd parity The transmitters can supply one, one-and-a-half, or two stop bits per character and can provide a break output at any time. The receiver break-detection logic interrupts the CPU both at the start and at the end of a received break. Reception is protected from spikes by a transient spike-rejection mechanism that checks the signal one-half a bit time after a Low level is detected on the receive data input (RxDA or RxDB pins). If the Low does not persist (a transient), the character assembly process does not start.
Functional Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
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Framing errors and overrun errors are detected and buffered together with the partial character on which they occur. Vectored interrupts allow fast servicing or error conditions using dedicated routines. A built-in checking process avoids the interpretation of a framing error as a new start bit. A framing error results in the addition of one-half a bit time to the point at which the search for the next start bit begins. The SCC does not require symmetric transmit and receive clock signals - a feature allowing use of the wide variety of clock sources. The transmitter and receiver handle data at a rate supplied to the receive and transmit clock inputs. In Asynchronous modes, the SYNC pin may be programmed as an input used for functions such as monitoring a ring indicator. Synchronous Modes The SCC supports both byte and bit-oriented synchronous communication. Synchronous byte-oriented protocols are handled in several modes. They allow character synchronization with a 6-bit or 8bit sync character (Monosync), and a 12-bit or 16-bit synchronization pattern (Bisync), or with an external sync signal. Leading sync characters are removed without interrupting the CPU. 5- or 7-bit synchronous characters are detected with 8- or 16-bit patterns in the SCC by overlapping the larger pattern across multiple incoming synchronous characters as indicated in Figure 10.
7 Bits
SYNC
SYNC
SYNC
Data
Data
Data
Data
8
16
Figure 10. Detecting 5- or 7-Bit Synchronous Characters
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
29
CRC checking for Synchronous byte-oriented modes is delayed by one character time so that the CPU may disable CRC checking on specific characters This feature permits the implementation of protocols such as IBM Bisync. Both CRC-16 (X16 + X15 + X2 +1) and CCITT (X16 + X12 + X5 + 1) error-checking polynomials are supported. Either polynomial may be selected in all Synchronous modes. Users may preset the CRC generator and checker to all 1's or all 0's. The SCC also provides a feature that automatically transmits CRC data when no other data is available for transmission. This feature allows for high speed transmissions under DMA control, with no need for CPU intervention at the end of a message. When there is no data or CRC to send in Synchronous modes, the transmitter inserts 6-,8-, or 16-bit sync characters, regardless of the programmed character length. SDLC Mode The SCC supports Synchronous bit-oriented protocols, such as SDLC and HDLC, by performing automatic flag sending, zero insertion, and CRC generation. A special command is used to abort a frame in transmission. At the end of a message, the SCC automatically transmits the CRC and trailing flag when the transmitter underruns. The transmitter may also be programmed to send an idle line consisting of continuous flag characters or a steady marking condition. If a transmit underrun occurs in the middle of a message, an external/status interrupt warns the CPU of this status change, issueing an abort. The SCC may also be programmed to send an abort itself in case of an underrun, relieving the CPU of this task. One to eight bits per character can be sent, allowing reception of a message with no prior information about the character structure in the information field of a frame.
Functional Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
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The receiver automatically acquires synchronization on the leading flag of a frame in SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can also be programmed). The receiver can be programmed to search for frames addressed by a single byte (or four bits within a byte) of a user-selected address or to a global broadcast address. In this mode, frames not matching either the user-selected or broadcast address are ignored. The number of address bytes are extended under software control For receiving data, an interrupt on the first received character, or an interrupt on every character, or on special condition only (endof-frame) can be selected The receiver automatically deletes all 0's inserted by the transmitter during character assembly CRC is also calculated and is automatically checked to validate frame transmission. At the end of transmission, the status of a received frame is available in the status registers. In SDLC mode, the SCC must be programmed to use the SDLC CRC polynomial, but the generator and checker may be preset to all 1's or all 0's. The CRC inverts before transmission and the receiver checks against the bit pattern 0001110100001111. NRZ, NRZI or FM coding may be used in any 1 x mode The parity options available In Asynchronous modes are available in Synchronous modes. SDLC Loop Mode The SCC supports SDLC Loop mode in addition to normal SDLC. In an SDLC Loop, a primary controller station manages the message traffic flow on the loop and any number of secondary stations. In SDLC Loop mode, the SCC performs the functions of a secondary station while an SCC operating in regular SDLC mode acts as a controller (Figure 11). SDLC loop mode can be selected by setting WR10 bit D1.
PS011701-0701
Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
31
Controller
Secondary #1
Secondary #4
Secondary #2
Secondary #3
Figure 11. An SDLC Loop
A secondary station in an SDLC Loop is always listening to the messages sent around the loop and, in fact, passes these messages to the rest of the loop by retransmitting them with a one-bittime delay. The secondary station places its own message on the loop only at specific times. The controller signals that secondary stations can transmit messages by sending a special character, called an EOP (End Of Poll), around the loop. The EOP character is the bit pattern 11111110. Because of zero insertion during messages, this bit pattern is unique and easily recognized. When a secondary station contains a message to transmit and recognizes an EOP on the line, it changes the last binary 1 of the EOP to a 0 before transmission. This change has the effect of turning the EOP into a flag sequence. The secondary station now places its message on the loop and terminates the message with an EOP. Any secondary stations further down the loop with messages to transmit append their messages to the message of the first secondary station by the same process. Any secondary stations without messages to send echo the incoming message and are
Functional Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
32
prohibited from placing messages on the loop (except when recognizing an EOP). In SDLC Loop mode, NRZ, NRZI, and FM coding may all be used. The SCC's ability to receive high speed back-to-back SDLC frames is maximized by a 10- deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides the DMA the ability to continue to transfer data into memory so that the CPU can examine the message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored. The byte count and status bits are accessed through Read Registers 6 and 7. Read Registers 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10 x 19 status FIFO is separate from the 3-byte receive data FIFO. Baud Rate Generator Each channel in the SCC contains a programmable Baud Rate Generator. Each generator consists of two 8-bit time constant registers that form a 16-bit time constant, a 16-bit down counter, and a flip-flop on the output producing a square wave. On start-up, the output flip-flop is set in a High state, the value in the time constant register is loaded into the counter, and the counter starts counting down. The output of the Baud Rate Generator toggles when reaching 0, the value in the time constant register is loaded into the counter, and the process is repeated. The time constant may be changed at any time, but the new value does not take effect until the next load of the counter. The output of the Baud Rate Generator may be used as either the transmit clock, the receive clock, or both. It can also drive the Digital Phase-locked loop (see next section). If the receive clock or transmit clock is not programmed to come from the TRxC pin, the output of the Baud Rate Generator may be echoed out through the TRxC pin. The following formula relates the time constant to the baud rate where PCLK or RTxC is the Baud
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
33
Rate Generator input frequency in Hertz. The clock mode is 1, 16, 32, or 64, as selected in Write Register 4, bits D6 and D7. Synchronous operation modes select 1 and Asynchronous modes select 16, 32 or 64.
PCLK or RTxC Frequency 2(Baud Rate)(Clock Rate)
Time Constant =
-2
Digital Phase-Locked Loop The SCC contains a Digital Phase-Locked Loop (DPLL) to recover clock information from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is nominally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with the data stream, to construct a clock for the data. This clock is used as the SCC receive clock, the transmit clock, or both. When the DPLL is selected as the transmit clock source, it provides a jitter-free clock output that is the DPLL input frequency divided by the appropriate divisor for the selected encoding technique. For NRZI encoding, the DPLL counts the 32x clock to create nominal bit times. As the 32x clock is counted, the DPLL is searching the incoming data stream for edges (either 1 to 0, or 0 to 1). Whenever an edge is detected, the DPLL makes a count adjustment (during the next counting cycle), producing a terminal count closer to the center of the bit cell. For FM encoding, the DPLL again counts from 0 to 31, but with a cycle corresponding to two bit times. When the DPLL is locked, the clock edges in the data stream occur between counts 15 and 16 and between counts 31 and 0. The DPLL looks for edges only during a time centered on the 15 to 16 counting transition.
Functional Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
34
The 32x clock for the DPLL can be programmed to come from either the RTxC input or the output of the Baud Rate Generator. The DPLL output may be programmed to be echoed out of the SCC through the TRxC pin (if this pin is not being used as an input). Data Encoding The SCC may be programmed to encode and decode the serial data in four different methods (Figure 12). In NRZ encoding, a 1 is represented by a High level and a 0 is represented by a Low level. In NRZI encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. In FM1 (more properly, bi-phase mark), a transition occurs at the beginning of every bit cell. A 1 is represented by an additional transition at the center of the bit cell and a 0 is represented by no additional transition at the center of the bit cell. In FM0 (bi-phase space), a transition occurs at the beginning of every bit cell. A 0 is represented by an additional transition at the center of the bit cell, and a 1 is represented by no additional transition at the center of the bit cell. In addition to these four methods, the SCC can be used to decode Manchester (bi-phase level) data by using the DPLL in the FM mode and programming the receiver for NRZ data. Manchester encoding always produces a transition at the center of the bit cell. If the transition is 0 to 1, the bit is a 0. If the transition is 1 to 0, the bit is a 1.
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
35
Data NRZ
1
1
0
0
1
0
NRZI
FM1
FM0
Manchester
Figure 12. Data Encoding Methods
Auto Echo and Local Loopback The SCC is capable of automatically echoing everything it receives. This feature is useful mainly in Asynchronous modes, but works in Synchronous and SDLC modes as well. Auto Echo mode (Tx0 is Rx0) is used with NRZI or FM encoding with no additional delay because the data stream is not decoded before retransmission. In Auto Echo mode, the CTS input is ignored as a transmitter enable (although transitions on this input can still cause interrupts if programmed to do so). In this mode, the transmitter is actually bypassed and the programmer is responsible for disabling transmitter interrupts and WAIT/REQUEST on transmit. The SCC is also capable of local loopback. In this mode, TxD or RxD is similar to Auto Echo mode. However, in Local Loopback mode the internal transmit data is tied to the internal receive data and RxD is ignored (except to be echoed out through TxD). The CTS and DCD inputs are also ignored as transmit and receive enables. However, transitions on these inputs can still cause inter-
Functional Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
36
rupts. Local Loopback works in Asynchronous, Synchronous and SDLC modes with NRZ, NRZI or FM coding of the data stream. SDLC FIFO Frame Status FIFO Enhancement The SCC's ability to receive high speed back-to-back SDLC frames is maximized by a 10- deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides the DMA the ability to continue to transfer data into memory so that the CPU can examine the message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored. The byte count and status bits are accessed through Read Registers 6 and 7. Read Registers 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10x19 status FIFO is separate from the 3-byte receive data FIFO. When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for the SDLC frame are stored in the 10 x 19 bit status FIFO. This arrangement allows the DMA controller to transfer the next frame into memory while the CPU verifies that the message was properly received. Summarizing the operation; data is received, assembled, and loaded into the eight byte FIFO before being transferred to memory by the DMA controller. When a flag is received at the end of an SDLC frame, the frame byte count from the 14-bit counter and five status bits are loaded into the status FIFO for verification by the CPU. The CRC checker automatically resets in preparation for the next frame which can begin immediately. Since the byte count and status are saved for each frame, the message integrity is verified at a later time. Status information for up to 10 frames is stored before a status FIFO overrun occurs. If a frame is terminated with an ABORT, the byte count is loaded to the status FIFO and the counter resets for the next frame.
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
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FIFO Detail For a better understanding of the FIFO operation details, refer to the block diagram in Figure 13. Enable/Disable This FIFO is implemented is enabled when WR15, bit D2, is set and the SCC is in the SDLC/HDLC mode. Otherwise, the status register contents bypass the FIFO and go directly to the bus interface (the FIFO pointer logic is reset either when disabled or through a channel or power-on reset). When the FIFO mode is disabled, the SCC is downward compatible with the NMOS Z8530. The FIFO mode is disabled on power-up (WR15 D2 is set to 0 on reset). The effects of backward compatibility on the register set are that RR4 is an image of RR0, RR5 is an image of RR1, RR6 is an image of RR2 and RR7 is an image of RR3. For the details of the added registers, refer to Figure 16. The status of the FIFO Enable signal is obtained by reading RR15, bit D2. If the FIFO is enabled, the bit is set to 1; otherwise, it resets. Read Operation When WR15 bit D2 sets and the FIFO is not empty, the next read to status register RR1 or registers RR7 and RR6, is from the FIFO. Reading status register RR1 causes one location of the FIFO to become empty. Status is read after reading the byte count, otherwise the count is incorrect. Before the FIFO underflows, it is disabled. In this case, the multiplexer is switched allowing status to read directly from the status register. Reads from RR7 and RR6 contain bits that are undefined. Bit D6 of RR7 (FIFO Data Available) determines if status data is coming from the FIFO or directly from the status register, which sets to 1 when the FIFO is not empty. Not all status bits are stored in the FIFO. The All Sent, Par-
Functional Description
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
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ity, and EOF bits bypass the FIFO. Status bits sent through the FIFO are Residue Bits (3), Overrun, and CRC Error.
Frame Status FIFO Circuitry
SCC Status Reg Residue Bits (3) Overrun, CRC Error Reset on Flag Detect Byte Counter Increment on Byte Detection Enable Count in SDLC End of Frame Signal 5 Bits FIFO Array 10 Deep by 19 Bits Wide 14 Bits Status Read Comp Tail Pointer 4-Bit Counter Head Pointer 4-Bit Counter 4-Bit Comparator Over 5 Bits EOF = 1 6 Bits 8 Bits Equal
RR1
6-Bit MUX
EN
2 Bits
6 Bits RR1
Bit 7 Bit 6
Bits 5-0
RR6
FIFO Enable
Interface to SCC
RR7 D5-D0 + RR6 D7-D0 Byte Counter Contains 14 bits for a 16 KByte maximum count RR7 D6 FIFO Data available status bit Status Bit set to 1 When reading from FIFO RR7 D7 FIFO Overflow Status Bit MSB pf RR(7) is set on Status FIFO overflow
WR(15) Bit 2 Set Enables Status FIFO
In SDLC Mode the following definitions apply - All Sent bypasses MUX and equals contents of SCC Status Register - Parity Bits bypasses MUX and does the same - EOF is set to 1 whenever reading from the FIFO
Figure 13. SDLC Frame Status FIFO
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Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
39
The sequence for operation of the byte count and FIFO logic is to read the registers in the following order. RR1, RR6, and RR1 (reading RR6 is optional). Additional logic prevents the FIFO from being emptied by multiple reads from RR1. The read from RR1 latches the FIFO empty/full status bit (06) and steers the status multiplexer to read from the SCC megacell instead of the status FIFO (since the status FIFO is empty). The read from RR1 allows an entry to be read from the FIFO (if the FIFO was empty, logic was added to prevent a FIFO underflow condition). Write Operation When the end of an SDLC frame (EOF) is received and the FIFO is enabled, the contents of the status and byte-count registers are loaded into the FIFO. The EOF signal is used to increment the FIFO. If the FIFO overflows, RR7, bit D7 (FIFO Overflow) sets to indicate the overflow. This bit and the FIFO control logic is reset by disabling and re-enabling the FIFO control bit (WR15, bit 02). For details of FIFO control timing during an SDLC frame, refer to Figure 14.
0 F A D D D D C 7 C 0 F 0 F A D D D D C 7 C 0 F
Internal Byte Strobe Increments Counter Don't Load Counter On 1st Flag Reset Byte Counter Here Reset Byte Counter Load Counter Into FIFO and Increment PTR
Internal Byte Strobe Increments Counter Reset Byte Counter Reset Byte Counter Load Counter Into FIFO and Increment PTR
Figure 14. SDLC Byte Counting Detail
Functional Description
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
40
Programming
The SCC contains write registers in each channel that are programmed by the system separately to configure the functional personality of the channels.
Z85C30
In the SCC, the data registers are directly addressed by selecting a High on the D/C pin. With all other registers (except WR0 and RR0), programming the write registers requires two write operations and reading the read registers requires both a write and a read operation. The first write is to WR0 and contains three bits that point to the selected register. The second write is the actual control word for the selected register, and if the second operation is read, the selected read register is accessed All of the SCC registers, including the data registers, may be accessed in this fashion. The pointer bits are automatically cleared after the read or write operation so that WR0 (or RR0) is addressed again.
Z80C30
All SCC registers are directly addressable. A command issued in WR0B controls how the SCC decodes the address placed on the address/data bus at the beginning of a Read or Write cycle. In the Shift Right mode, the channel select A/B is taken from AD0 and the state of AD5 is ignored. In the Shift Left mode, the channel select A/B is taken from AD5 and the state of AD0 is ignored. AD7 and AD6 are always ignored as address bits and the register address occupies AD4-AD1.
PS011701-0701
Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
41
Z85C30/Z80C30 Setup
Initialization The system program first issues a series of commands to initialize the basic mode of operation. This is followed by other commands to qualify conditions within the selected mode. For example, in the Asynchronous mode, character length, clock rate, number of stop bits, and even or odd parity must be set first. The interrupt mode is set, and finally, the receiver and transmitter are enabled. Write Registers The SCC contains 15 write registers for the 80C30, while there are 16 for the 85C30 (one more additional write register if counting the transmit buffer) in each channel. These write registers are programmed separately to configure the functional "personality" of the channels. There are two registers (WR2 and WR9) shared by the two channels that are accessed through either of them. WR2 contains the interrupt vector for both channels, while WR9 contains the interrupt control bits and reset commands. Figures 15 through 18 depict the format of each write register.
Functional Description
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
42
Write Register 0 (non-multiplexed bus mode) D7 D6 D5 D4 D3 D2 D1 D0
Write Register 1 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1
0 1 0 1
000 001 010 011 100 101 110 111 Null Code Reset Rx CRC Checker Reset Tx CRC Generator Reset Tx Underrun/EOM Latch
0 0 0 Register 0 0 0 1 Register 1 0 1 0 Register 2 0 1 1 Register 3 1 0 0 Register 4 1 0 1 Register 5 1 1 0 Register 6 1 1 1 Register 7 0 0 0 Register 8 0 0 1 Register 9 0 1 0 Register 10 0 1 1 Register 11 * 1 0 0 Register 12 1 0 1 Register 13 1 1 0 Register 14 1 1 Register 15 Null Code Point High Reset Ext/Status Interrupts Send Abort (SDLC) Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS
Ext Int Enable Tx Int Enable Parity is Special Condition 0 0 1 1 0 1 0 1 Rx Int Disable Rx Int on First Character or Special Condition Int on all Rx Characters or Special Condition Rx Int on Special Condition Only WAIT/DMA Request on Receive /Transmit WAIT/DMA Request Function WAIT/DMA Request Write Register 2 D7 D6 D5 D4 D3 D2 D1 D0 V0 V1 V2 V3 V4 V5 V6 Interrupt Vector
* With Point High Command
Write Register 0 (multiplexed bus mode) D7 D6 D5 D4 D3 D2 D1 D0 Write Register 3 0 0 1 1 0 1 0 1 Null Code Null Code Select Shift Left Mode Select Shift Right Mode 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Null Code Null Code Reset Ext/Status Interrupts Send Abort Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS D7 D6 D5 D4 D3 D2 D1 D0 *
V7
Rx Enable Sync Character Load Inhibit Address Search Mode (SDLC) Rx CRC Enable Enter Hunt Mode Auto Enables 0 0 1 1 0 1 0 1 Rx 5 Bits/Character Rx 7 Bits/Character Rx 6 Bits/Character Rx 8 Bits/Character
Null Code Reset Rx CRC Checker Reset Tx CRC Checker Reset Tx Underrun/EOM Latch
* B Channel Only
Figure 15. Write Register Bit Functions
PS011701-0701
Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
43
Write Register 4 D7 D6 D5 D4 D3 D2 D1 D0
Write Register 5 D7 D6 D5 D4 D3 D2 D1 D0
Parity Enable Parity EVEN/ODD 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sync Modes Enable 1 Stop Bit/Character 1 1/2 Stop Bits/Character 2 Stop Bits/Character 0 0 1 1 0 1 0 1 Tx 5 Bits (or Less)/Character Tx 7 Bits/Character Tx 6 Bits/Character Tx 8 Bits/Character
Tx CRC Enable RTS SDLC/CRC-16 Tx Enable Send Break
8-Bit Sync Character 16-Bit Sync Character SDLC Mode (01111110 Flag) External Sync Mode
DTR 0 0 1 1 0 X1 Clock Mode 1 X16 Clock Mode 0 X32 Clock Mode 1 X64 Clock Mode
Figure 16. Write Register Bit Functions
Functional Description
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
44
Write Register 6 D7 D6 D5 D4 D3 D2 D1 D0
Sync7 Sync1 Sync7 Sync3 ADR7 ADR7
Sync6 Sync0 Sync6 Sync2 ADR6 ADR6
Sync5 Sync5 Sync5 Sync1 ADR5 ADR5
Sync4 Sync4 Sync4 Sync0 ADR4 ADR4
Sync3 Sync3 Sync3 1 ADR3 x
Sync2 Sync2 Sync2 1 ADR2 x
Sync1 Sync1 Sync1 1 ADR1 x
Sync0 Sync0 Sync0 1 ADR0 x
Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC SDLC (Address Range)
Write Register 7 D7 D6 D5 D4 D3 D2 D1 D0
Sync7 Sync6 Sync5 Sync4 Sync15 Sync14 Sync11 Sync10 0 1
Sync5 Sync3 Sync13 Sync9 1
Sync4 Sync2 Sync12 Sync8 1
Sync3 Sync1 Sync11 Sync7 1
Sync2 Sync1 Sync0 x Sync0 x Sync10 Sync9 Sync8 Sync6 Sync5 Sync4 1 1 0
Monosync, 8 Bits Monosync, 6 Bits Bisync, 16 Bits Bisync, 12 Bits SDLC
WR 7' Prime (85C30 only) D7 D6 D5 D4 D3 D2 D1 D0
Auto Tx Flag Auto EOM Reset Auto RTS Deactivation Force TxD High DTR/REQ Fast Mode Complete CRC Reception Extended Read Enable Reserved (Program as 0)
Figure 17. Write Register Bit Functions
PS011701-0701
Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
45
Write Register 9 D7 D6 D5 D4 D3 D2 D1 D0
Write Register 9 D7 D6 D5 D4 D3 D2 D1 D0
VIS NV DLC MIE Status High/Status Low Software INTACK Enable 0 0 1 1 0 1 0 1 No Reset Channel Reset B Channel Reset A Force Hardware Reset Write Register 13 D7 D6 D5 D4 D3 D2 D1 D0 Write Register 9 D7 D6 D5 D4 D3 D2 D1 D0
TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Lower Byte of Time Constant
TC8 TC9 6-Bit/8-Bit Sync Loop Mode Abort/Flag on Underrun Mark/Flag Idle Go Active on Poll 0 0 1 1 0 NRZ 1 NRZI 0 FM1 (Transition = 1) 1 FM1 (Transition = 0) CRC Preset I/O BR Generator Enable Write Register 11 D7 D6 D5 D4 D3 D2 D1 D0 BR Generator Source DTR/Request Function Auto Echo 0 0 1 1 0 1 0 1 TRxC Out = Xtal Output TRxC Out = Transmit Clock TRxC Out = BR Generator Output TRxC Out = DPLL Output TRxC O/I 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Transmit Clock = RTxC Pin Transmit Clock = TRxC Pin Transmit Clock = BR Generator Output Transmit Clock = DPLL Output Local Loopback 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Null Command Enter Search Mode Reset Missing Clock Disable DPLL Set Source = BR Generator Set Source = RTxC Set FM Mode Set NRZI Mode TC10 TC11 TC12 TC13 TC14 TC15 Write Register 14 D7 D6 D5 D4 D3 D2 D1 D0 Upper Byte of Time Constant
Write Register 15 Receive Clock = RTxC Pin Receive Clock = TRxC Pin Receive Clock = BR Generator Output Receive Clock = DPLL Output RTxC Xtal/No Xtal D7 D6 D5 D4 D3 D2 D1 D0
0 Zero Count IE SDLC FIFO Enable DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE
Figure 18. Write Register Bit Functions
Functional Description
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
46
Read Registers The SCC contains ten read registers (eleven, counting the receive buffer (RR8) in each channel). Four of these may be read to obtain status information (RR0, RR1, RR10, and RR15). Two registers (RR12 and RR13) are read to learn the Baud Rate Generator time constant. RR2 contains either the unmodified interrupt vector (Channel A) or the vector modified by status information (Channel B). RR3 contains the Interrupt Pending (IP) bits (Channel A only -, Figure 19). RR6 and RR7 contain the information in the SDLC Frame Status FIFO, but is only read when WR15 D2 is set (Figures 19 and 20).
PS011701-0701
Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
47
Read Register 0 D7 D6 D5 D4 D3 D2 D1 D0
Read Register 3 D7 D6 D5 D4 D3 D2 D1 D0
Rx Character Available Zero Count Tx Buffer Empty DCD Sync/Hunt CTS Tx Underrun/EOM Break/Abort Read Register 1 D7 D6 D5 D4 D3 D2 D1 D0 * Always 0 in B Channel Read Register 10 D7 D6 D5 D4 D3 D2 D1 D0 All Sent Residue Code 2 Residue Code 1 Residue Code 0 Parity Error Rx Overrun Error CRC/Framing Error End of Frame (SDLC)
Channel B Ext/Status IP Channel B Tx IP Channel B Rx IP Channel A Ext/Status IP Channel A Tx IP Channel A Rx IP 0 0 *
0 On Loop 0 0 Loop Sending 0 Two Clocks Missing One Clocks Missing
Read Register 2 D7 D6 D5 D4 D3 D2 D1 D0 Read Register 12 D7 D6 D5 D4 D3 D2 D1 D0 V0 V1 V2 V3 V4 V5 V6 V7 * Modified in B Channel Interrupt Vector * TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Lower Byte of Time Constant
Figure 19. Read Register Bit Functions
Functional Description
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
48
Read Register 13 D7 D6 D5 D4 D3 D2 D1 D0
Read Register 15 D7 D6 D5 D4 D3 D2 D1 D0
TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 Upper Byte of Time Constant
0 Zero Count IE 0 DCD IE Sync/Hunt IE CTS IE Tx Underrun/EOM IE Break/Abort IE
Figure 20. Read Register Bit Functions
Z85C30 Timing
The SCC generates internal control signals from the WR and RD that are related to PCLK. PCLK has no phase relationship with WR and RD, the circuitry generating the internal control signals provides time for meta-stable conditions to disappear. This gives rise to a recovery time related to PCLK.The recovery time applies only between bus transactions involving the SCC. The recovery time required for proper operation is specified from the falling edge of WR or RD in the first transaction involving the SCC to the falling edge of WR or RD in the second transaction involving the SCC. This time must be at least 3 PCLKs regardless of which register or channel is being accessed. Read Cycle Timing Figure 21 illustrates Read cycle timing. Addresses on A/ B and D/C and the status on INTACK must remain stable throughout the cycle. If CE falls after RD falls, or if CE rises before RD rises, the effective RD is shortened.
PS011701-0701
Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
49
A/B, D/C
Address Valid
INTACK
CE
RD
D7-D0
Data Valid
Figure 21. Read Cycle Timing
Write Cycle Timing Figure 22 illustrates Write cycle timing. Addresses on A/B and D/C and the status on INTACK must remain stable throughout the cycle. If CE falls after WR falls, or if CE rises before WR rises, the effective WR is shortened. Data must be valid before the falling edge of WR.
Functional Description
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
50
A/B, D/C
Address Valid
INTACK
CE
WR
D7-D0
Data Valid
Figure 22. Write Cycle Timing
Interrupt Acknowledge Cycle Timing Figure 23 illustrates Interrupt Acknowledge cycle timing. Between the time INTACK goes Low and the falling edge of RD, the internal and external IEI/IEO daisy chains settle. If there is an interrupt pending in the SCC and IEI is High when RD falls, the Acknowledge cycle is intended for the SCC. In this case, the SCC may be programmed to respond to RD Low by placing its interrupt vector on D7-D0. It then sets the appropriate Interrupt-Under-Service latch internally. If the external daisy chain is not used, AC parameter #38 is required to settle the interrupt priority daisy chain internal to the SCC. If the external daisy chain is used, the user should follow the equation in AC Characteristics, Read/Write Timing Table 5, Note 5 starting on Page 62 for calculating the required daisy-chain settle time.
PS011701-0701
Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
51
INTACK
RD
D7-D0 Vector
Figure 23. Interrupt Acknowledge Cycle Timing
Z80C30 Timing
The SCC generates internal control signals from AS and DS that are related to PCLK. Because PCLK has no phase relationship with AS and DS, the circuitry generating these internal control signals must provide time for metastable conditions to disappear. This gives rise to a recovery time related to PCLK. The recovery time applies only between bus transactions involving the SCC The recovery time required for proper operation is specified from the falling edge of DS in the first transaction involving the SCC to the falling edge of DS in the second transaction involving the SCC. Read Cycle Timing Figure 24 illustrates Read cycle timing. The address on AD7-AD0 and the state of CS0 and INTACK are latched by the rising edge of AS. R/W must be High to indicate a Read cycle. CS1 must also be High for the Read cycle to occur. The data bus drivers in the SCC are then enabled while DS is Low.
Functional Description
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
52
AS
CS0
INTACK
AD7-AD0
Address
Data Valid
R/W
CS1
DS
Figure 24. Read Cycle Timing
Write Cycle Timing Figure 25 illustrates Write cycle timing. The address on AD7-AD0 and the state of CS0 and INTACK are latched by the rising edge of AS. R/W must be Low to indicate a Write cycle. CS1 must be High for the Write cycle to occur DS Low strobes the data into the SCC.
PS011701-0701
Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
53
AS
CS0
INTACK
AD7-AD0
Address
Data
R/W
CS1
DS
Figure 25. Write Cycle Timing
Interrupt Acknowledge Cycle Timing Figure 26 illustrates Interrupt Acknowledge cycle timing. The address on AD7-AD0 and the state of CS0 and INTACK are latched by the rising edge of AS. If INTACK is Low, the address and CS0 are ignored. The state of the R/W and CS1 are also ignored for the duration of the Interrupt Acknowledge cycle. Between the rising edge of AS and the falling edge of DS, the internal and external IEI/IEO daisy chains settle. If there is an interrupt pending in the SCC, and IEI is High when DS falls, the Acknowledge cycle was intended for the SCC. In this case, the SCC is pro-
Functional Description
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
54
grammed to respond to RD Low by placing its interrupt vector on D7-D0 and internally setting the appropriate Interrupt-Under-Service latch.
AS
CS0
(Ignored)
INTACK
AD7-AD0
(Ignored)
Vector
DS
Figure 26. Interrupt Acknowledge Cycle Timing
PS011701-0701
Functional Description
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
55
Electrical Characteristics
Absolute Maximum Ratings
Vcc Supply Voltage range TA Operating Ambient Temperature Storage Temperature -0.3V to +7.0V See Ordering Information 65C to +150C
Voltages on all pins with respect to GND -3V to VCC +0.3V
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only. Operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Standard Test Conditions
The DC Characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin. Refer to Figures 27 and 28.
* * *
+4.50V Vcc + 5.50V GND = 0V TA as specified in Ordering Information
PS011701-0701
Absolute Maximum Ratings
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
56
2.1 K
From Output Under Test
100 pF
250 A
Figure 27. Standard Test Load
2.2 K
From Output
50 pF
Figure 28. Open-Drain Test Load
PS011701-0701
Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
57
Capacitance
Table 3 lists the input, output, and bidirectional capacitance.
Table 3. Capacitance Symbol CIN COUT CI/O Parameter Input Capacitance Output Capacitance Bidirectional Capacitance Min Max 10 15 20 Unit pFa pF pF Test Condition Unmeasured Pins Returned to Groundb
a. pF = 1 MHz, over specified temperature range. b. Unmeasured pins returned to Ground.
Miscellaneous
Gate Count is 6800
DC Characteristics
Z80C30/Z85C30
Table 4 lists the dc characteristics for the Z80C30/Z85C30 devices.
Electrical Characteristics
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
58
Table 4. Z80C30/Z85C30 DC Characteristics Symbol Parameter VIH VIL VOH1 VOH2 VOL IIL IOL ICC1 Input High Voltage Input Low Voltage Min 2.2 -0.3 Typ Max VCC +0.3a 0.8 Unit Condition V V V V 0.4 V A A mA IOH = -1.6 mA IOH = -250 A IOL = +2.0 mA 0.4 VIN + 24V 0.4 VOUT + 24V VCC = 5V VIH = 4.8 VIL = 0 Crystal Oscillator off Current for each OSC in addition to ICC1
Output High 2.4 Voltage Output High VCC -0.8 Voltage Output Low Voltage Input Leakage Output Leakage VCC Supply Currentb 7 9
10.0 10.0
12 (10 MHz)
15 (16.384 MHz mA mA
ICCOSC
Crystal OSC Currentc
4
a. b. c.
VCC = SV t10% unless otherwise specified, over specified temperature range. Typical ICC was measured with oscillator off. No ICC (OSC) max is specified due to dependency on external circuit and frequency of oscillation.
PS011701-0701
Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
59
AC Characteristics
Z85C30 Read/Write Timing Diagrams
Figures 29 through 32 illustrate the Z85C30 read/write timing diagrams. Table 5 lists the Z85C30 timing parameters.
Electrical Characteristics
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
60
1
PCLK 2 3 6 A/B, D/C 7 9 INTACK 10 13 CE 18 16 RD 19 22 D7-D0 Read Active 23 24 25 27 WR 28 D7-D0 Write 31 29 W/REQ Wait 30 26 Valid 17 20 21 11 14 15 12 10 5 4
32 35
W/REQ Request DTR/REQ Request 33 34 36 INT 37
Figure 29. Z85C30 Read/Write Timing Diagram
PS011701-0701
Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
61
PCLK 10 INTACK 10 RD 24 23 D7-D0 38 Active 40 41 42 IEI 43 44 Valid 26 38 14 15
IEO 45 INT
Figure 30. Z85C30 Interrupt Acknowledge Timing Diagram
49b
49b
PCLK
CE
49a
RD or WR
Figure 31. Z85C30 Cycle Timing Diagram
Electrical Characteristics
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
62
WR 48 RD 47 48
Figure 32. Z85C30 Reset Timing Diagram
Table 5. Z85C30 Read/Write Timing 8.5 MHz No Symbol 1 2 3 4 5 6 7 8 9 10 TwPCI TwPCh TfPC TrPC TcPC TsA(WR) ThA(WR) TsA(RD) ThA(RD) TsiA(PC) Parameter PCLK Low Width PCLK High Width PCLK Fall Time PCLK Rise Time PCLK Cycle Time 118 Min 45 45 Max 2000 2000 10 10 4000 100 50 0 50 0 20 10 MHz Min 40 40 Max 2000 2000 10 10 4000 61 35 0 35 0 15 16 MHz Min Max 26 26 2000 2000 5 5 4000
Address to WR Fall 66 Setup Time Address to WR Rise Hold Time 0
Address to RD Fall 66 Setup Time Address to RD Rise 0 Hold Time INTACK to PCLK Rise Setup Time 20
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
63
Table 5. Z85C30 Read/Write Timing (continued) 8.5 MHz No Symbol 11 12 13 14 15 16 17 18 19 20 21 22 23 TsiAi(WR)a ThIA(WR) TsiAi(RD)1 ThIA(RD) ThIA(PC) TsCEI(WR) ThCE(WR) TsCEh(WR) TsCEI(RD)1 ThCE(RD)1 TsCEh(RD)1 TwRDI1 TdRD(DRA) Parameter Min Max 10 MHz Min 120 0 120 0 30 0 0 50 0 0 50 125 0 30 70 0 Max 16 MHz Min Max 70 0 70 0 15 0 0 30 0 0
INTACK to WR Fall 140 Setup Time INTACK to WR Rise Hold Time 0
INTACK to RD Fall 140 Setup Time INTACK to RD Rise 0 Hold Time INTACK to PCLK Rise Hold Time 38
CE Low to WR Fall 0 Setup Time CE to WR Rise Hold Time 0
CE High to WR Fall 58 Setup Time CE Low to RD Fall Setup Time 0
CE to RD Rise Hold 0 Time CE High to RD Fall 58 Setup Time RD Low Width RD Fall to Read Data Active Delay 145 0
Electrical Characteristics
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
64
Table 5. Z85C30 Read/Write Timing (continued) 8.5 MHz No Symbol 24 25 26 27 28 29 30 31 32 33 34 TdRDr(DR) TdRDI(DR) TdRD(DRz) TdA(DR) TwWRI TdWR(DW) ThDW(WR) TdWR(W)b TdRD(W)2 Parameter RD Rise to Data Not Valid Delay RD Fall to Read Data Valid Delay RD Rise to Read Data Float Delay Addr to Read Data Valid Delay WR Low Width WR Fall to Write Data Valid Delay Write Data to WR Rise Hold Time WR Fall to Wait Valid Delay RD Fall to Wait Valid Delay 0 168 168 168 168 4TcPc 168 120 145 35 0 100 100 120 70 4TcPc 100 4TcPc 70 Min 0 135 38 210 125 35 0 50 50 70 Max 10 MHz Min 0 120 35 160 75 20 Max 16 MHz Min Max 0 70 30 100
TdWRf(REQ) WR Fall to W/REQ Not Valid Delay TdRDf(REQ)c RD Fall to W/REQ Not Valid Delay
35a TdWRr(REQ) WR Fall to DTR/ REQ Not Valid 35b TdWRr(REQ)3 WR Fall to DTR/ REQ Not Valid
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
65
Table 5. Z85C30 Read/Write Timing (continued) 8.5 MHz No Symbol 36 TdRDrrREQ) Parameter RD Rise to DTR/ REQ Not Valid Delay PCLK Fall to INT Valid Delay INTACK to RD Fall 145 (Ack) Delay RD (Acknowledge) 145 Width RD Fall (Ack) to Read Data Valid Delay 135 Min Max NA 10 MHz Min Max NA 16 MHz Min Max NA
37 38 39 40
TdPCrINT) TdIAirRD)d TwRDA TdRDA(DR)
500 90 125 120
320 50 75 70
175
41 42 43 44 45 46 47
TsiEI(RDA) ThIEI(RDA) TdIElrIEO) TdPC(IEO)
IEI to RD Fall (Ack) 95 Setup Time IEI to RD Rise (Ack) 0 Hold Time IEI to IEO Delay Time PCLK Rise to IEO Delay 95 195 480
80 0 80 175 320 15 15
50 0 45 80 200 10 10
TdRDA(INT)2 RD Fall to INT Inactive Delay TdRDrWRQ) TdWRQ(RD) RD Rise to WR Fall 15 Delay for No Reset WR Rise to RD Fall 15 Delay for No Reset
Electrical Characteristics
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
66
Table 5. Z85C30 Read/Write Timing (continued) 8.5 MHz No Symbol 48 TwRES Parameter Min Max 10 MHz Min 100 35TcPc 0 0 Max 16 MHz Min Max 75
WR and RD Low for 145 Reset Valid Access Recovery Time 3.5T 3.5TcPc cPc
49a Trce 49b Trcif
RD or WR Fall to 0 PC Fall Setup Time
a. b. c. d.
e. f.
Parameter does not apply to Interrupt Acknowledge transactions. Open-drain output, measured with open-drain test load. Parameter applies to enhanced Request mode oniy (WR7' D4 = 1). Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each device separating them in the daisy chain. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.
Figure 33 is the Z85C30 general timing diagram. Table 6 lists the Z85C30 general timing characteristics. Z85C30 system timing is shown in Figure 34 and described in Table 7. Table 8 provides Z85C30 read/write timing characteristics. Figures 35 through 37 illustrate Z80C30 read/write timing, interrupt acknowledge timing, and reset timing respectively. Table 9 provides Z80C30 read/write timing characteristics.
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
67
PCLK 1 W/REQ Request 2 W/REQ Wait CTS/TRxC, RTxC Receive 4 RxD 9 SYNC External CTS/TRxC, RTxC Transmit 8 5 6 7
3
10
11 TxD 13 CTS/TRxC Output 14 RTxC 16 17 CTS/TRxC 18 20 CTS/TRxC DCD 22 SYNC Input 22 22 22 19 15
12
Figure 33. Z85C30 General Timing Diagram
Electrical Characteristics
PS011701-0701
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
68
Table 6. Z85C30 General Timing Table 8.5 MHz No Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 TdPC(REQ) TdPC(W) TsRXC(PC) Parameter PCLK to W/REQ Valid PCLK to Wait Inactive RxC to PCLK Setup Timea,b N/A 0 150 0 125 0 25 -150 5TcPc N/A 200 200 200 150 50 150 50 488 120 40 120 40 400 150 150 140 80 15.6 80 15.6 244 Min Max 250 350 N/A 0 50 0 50 -100 5TcPc N/A 80 80 80 10 MHz Min 16 MHz Max 80 180 N/A 0
Max Min 150 250
TsRXD(RXCr) RxD to RxC Setup Time1 ThRXD(RxCr) RxD to /RXC Hold Time1 TsRXD(RXCf) RxD to /RXC Setup Time1,c
ThRXD(RXCf) RxD to /RXC Hold Time1,3 150 1 TsSY(RXC) ThSY(RXC) TsTXC(PC) SYNC to RxC Setup Time1 -200
SYNC to RxC Hold Time1 5TcPc TxC to PCLK Setup Timed,e
4,3
N/A
TdTXCf(TXD) TxC to TxD Delay4 TdTxCr(TXD) TxC to TxD Delay TdTXD(TRX)
TxD to TRxC Delay RTxC High Width
f
14a TwRTXh 14b TwRTXh(E) 15a TwRTXI 15b TwRTXI(E) 16a TcRTX
RTxC High Widthg TRxC Low Width
6
RTxC Low Width7 RTxC Cycle Time
6,h
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
69
Table 6. Z85C30 General Timing Table (continued) 8.5 MHz No Symbol 16b TcRTX(E) 17 18 19 20 21 22
a. b. c. d. e.
10 MHz Min 100
16 MHz Max
Parameter RTxC Cycle Time7 Crystal Osc. Periodi TRxC High Width6 TRxC Low Width6 TRxC Cycle Time6,8
Min 125 125 150 150 488
Max
Max Min 31.25 1000 62 180 80 244 70 70
TcRTXX TwTRXh TwTRXI TcTRX TwEXT TwSY
1000
100 120 120 400 120 120
1000
DCD or CTS Pulse Width 200 SYNC Pulse Width 200
f. g. h. i.
RxC is RTxC or TRxC, whichever is supplying the receive clock. Synchronization of RxC to PCLK is eliminated in divide by four operation. Parameter applies only to FM encoding/decoding. TxC is TRxC or /RTxC, whichever is supplying the transmit clock. External PCLK to RTxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation.TRxC and RTxC rise and fall times are identical to PCLK. Reference timing specs TfPC and TrPC.Tx and Rx input clock slew rates should be kept to a maximum of 30 nsec. All parameters related to input CLK edges should be referenced at the point at which the transition begins or ends, whichever is worst case. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are identical to case PCLK requirements. ENHANCED FEATURE -- RTxC used as input to internal DPLL only. The maximum receive or transmit data rate is 1/4 PCLK. Both RTxC and SYNC have 30 pF capacitors to ground connections.
Z80C30 general timing is shown in Figure 38 with parameters provided in Table 10. Z80C30 system timing is shown in Figure 39 with parameters provided in Table 11.
Electrical Characteristics
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
70
RTxC, TRxC Receive
W/REQ Request 1 W/REQ Wait 2 SYNC Output 3 INT 4 TRxC, RTxC Transmit
W/REQ Request 6 W/REQ Wait 6 DTR/REQ Request 7
INT 8 CTS, DCD
SYNC Input 9 INT 10
Figure 34. Z85C30 System Timing Diagram
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
71
Table 7. Z85C30 System Timing Table 8.5 MHz No Symbol 1 2 3 4 5 6 7 8 Parameter Min 8 8 47 Max 12 14 4 16 8 11 7 10 6 3 6 10 MHz Min 8 8 74 10 5 5 4 6 2 2 2 Max 12 14 7 16 8 11 7 10 6 3 6 10 5 5 4 6 2 2 2 16 8 11 7 10 6 3 6 16 MHz Min Max 8 8 12 14
TdRXC(REQ) RxC High to W/REQ Valida,b TdRXC(W) RxC High to Wait Inactive1,2,c
TdRdXC(SY) RxC High to SYNC Valid1,2 TsRXC(INT)
RxC High to INT Valid 1,2,3 10 5 5 4
TdTXC(REQ) TxC Low to W/REQ Valid2,d TdTXC(W) TxC Low to Wait Inactive2,3,4
TdTXC(DRQ) TxC Low to DTR/REQ Valid3,4 TdTXC(INT) SYNC to INT Valid 2,3 SYNC to INT Valid
2,3,e
TxC Low to INT Valid2,3,4 6 2 2 2
9a TdSY(INT) 9b TdSY(INT) 10 TdEXT(INT)
DCD or CTS to INT Valid2,3
a. b. c. d. e.
RxC is RTxC or TRxC, whichever is supplying the receive clock. Units equal to TcPc. Open-drain output, measured with open-drain test load. TxC is TRxC or RTxC whichever is supplying the transmit clock. Units equal to AS.
Electrical Characteristics
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
72
Table 8. Z85C30 Read/Write Timing 8.5 MHz No 1 2 3 4 5 6 7 8 9 10 Symbol TwPCI TwPCh TfPC TrPC TcPC Parameter PCLK Low Width PCLK High Width PCLK Fail Time PCLK Rise Time PCLK Cycle Time 118 Min 45 45 Max 2000 2000 10 10 4000 100 50 0 50 0 20 10 MHz Min 40 40 Max 2000 2000 10 10 4000 61 35 0 35 0 15 16 MHz Min 26 26 Max 2000 2000 5 5 4000
TsA(WR) Address to WR Fail Setup 66 Time ThA(WR) Address to WR Rise Hold 0 Time TsA(RD) Address to RD Fall Setup 66 Time 0 20
ThA(RD) Address to RD Rise Hold Time TsiA(PC) INTACK to PCLK Rise Setup Time
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
73
AS 4 CS0 7 CS1 4 14 INTACK 7 R/W Read 9 R/W Write 12 DS 12 AD7-AD0 Write 15 AD7-AD0 Read 15 22 24 W/REQ Wait 25 W/REQ Request 26 DTR/REQ Request 27 INT 44 PCLK 41 40 42 43 44 13 8
2
6
10
10
18
16 17 20
16 19 21 23
Figure 35. Z80C30 Read/Write Timing Diagram
Electrical Characteristics
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
74
AS 7 INTACK 8 DS 29 19 AD7-AD0 31 32 IEI 34 35 22 33 30 20
IEO 36 INT
Figure 36. Z80C30 Interrupt Acknowledge Timing Diagram
AS 37 38 35 DS
Figure 37. Z80C30 Reset Timing Diagram
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
75
Table 9. Z80C30 Read/Write Timinga 8 MHz No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol TwAS TdDS(AS) TsCSO(AS) ThCSO(AS) TsCS1(DS) ThCS1(DS) TsiA(AS) ThIA(AS) TsRWR(DS) ThRW(DS) Parameter AS Low Width DS Rise to AS Fall Delayb CS0 to AS Rise Setup Time CS0 to AS Rise Hold Time2 CS1 to DS Fall Setup Time
2 2
10 MHz Max Min 30 10 0 20 50 20 10 125 50 0 0 20 125 4TcPC 10 20 10 0 Max
Min 35 15 0 30 65 30
CS1 to DS Rise Hold Time2
INTACK to AS Rise Setup Time 10 INTACK to AS Rise Hold Time R/W (Read) to DS Fall Setup Time R/W to DS Rise Hold Time 150 65 0 0 30 150 4TcPC 10
TsRWW(DS) R/W (Write) to DS Fall Setup Time TdAS(DS) TwDSI TrC TsA(AS) ThA(AS) TsDW(DS) ThDW(DS) AS Rise to DS Fall Delay DS Low Width Valid Access Recovery Timec Address to AS Rise Setup Time2
Address to AS Rise Hold Time2 25 Write Data to DS Fall Setup Time Write Data to DS Rise Hold Time 15 0
Electrical Characteristics
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
76
Table 9. Z80C30 Read/Write Timinga (continued) 8 MHz No 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol TdDS(DA) TdDSr(DR) TdDSf(DR) TdAS(DR) TdDS(DRz) TdA(DR) TdDS(W) Parameter DS Fall to Data Active Delay Min 0 Max 10 MHz Min 0 0 140 250 40 260 170 170 4TcPC 500 250 150 140 80 80 225 125 120 120 190 35 210 160 160 4TcPC 500 Max
DS Rise to Read Data Not Valid 0 Delay DS Fall to Read Data Valid Delay AS Rise to Read Data Valid Delay DS Rise to Read Data Float Delayd Address Required Valid to Read Data Valid Delay DS Fall to Wait Valid Delaye
TdDSf(REQ) DS Fall to W/REQ Not Valid Delay TdDSr(REQ) DS Fall to DTR/REQ Not Valid Delay TdAS(INT) TdAS(DSA) TwDSA TdDSA(DR) TsiEI(DSA) AS Rise to INT Valid Delay5 AS Rise to DS Fall (Acknowledge) Delayf DS (Acknowledge) Low Width DS Fall (Acknowledge) to Read Data Valid Delay IEI to DS Fall (Acknowledge) Setup Time
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
77
Table 9. Z80C30 Read/Write Timinga (continued) 8 MHz No 33 34 35 36 37 38 39 40 41 42 43 44
a. b. c. d. e. f.
10 MHz Max Min 0 90 200 450 90 175 450 15 15 100 1000 1000 2000 10 10 40 40 100 1000 1000 2000 10 10 Max
Symbol ThIEI(DSA) TdIEI(IEO) TdAS(IEO) TdDSA(INT) TdDS(ASQ) TdASQ(DS) TwRES TwPCI TwPCh TcPC TrPC TfPC
Parameter IEI to DS Rise (Acknowledge) Hold Time IEI to IEO Delay AS Rise to IEO Delayg DS Fall (Acknowledge) to INT Inactive Delay5 DS Rise to AS Fall Delay for No Reset
Min 0
15
AS Rise to DS Fall Delay for No 20 Reset AS and DS Coincident Low for Reseth PCLK Low Width PCLK High Width PCLK Cycle Time PCLK Rise Time PCLK Fall Time 150 50 50 125
Units in nanoseconds (ns) unless otherwise noted. Parameter does not apply to Interrupt Acknowledge transactions. Parameter applies only between transactions involving the SCC. Float delay is defined as the time required for a 0.5V change in the output with a maximum DC load and a minimum AC load. Open-drain output, measured with open-drain test load. Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of TdAS(IEO) for the highest priority device in the daisy chain TsiEI(DSA) for the Z-SCC, and TdIElf(IEO) for each device separating them in the daisy chain.
Electrical Characteristics
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
78
g. h.
Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction. Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the ZSCC. All timing references assume 20V for a logic "1" and 08V for a logic "0".
Figure 38 displays Z80C30 general timing and Table 10 lists the associated general timing characteristics. Figure 39 displays the Z80C30 system timing with the associated parameters listed in Table 11.
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
79
PCLK 1 W/REQ Request 2 W/REQ Wait 3 RTxC, TRxC Receive 4 RxD 8 SYNC External 9 5 6 7
TRxC, RTxC Transmit
10 11 12
TxD 13 TRxC Output 14 RTxC 16 17 TRxC 18 20 CTS, DCD 22 SYNC Input 22 22 22 19 15
Figure 38. Z80C30 General Timing Diagram
Electrical Characteristics
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
80
Table 10. Z80C30 General Timinga 8 MHz No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16a 16b 17 18 Symbol TdPC(REQ) TsPC(W) TsRXC(PC) Parameter PCLK Low to W/REQ Valid PCLK Low to Wait Inactive RxC High to PCLK High Setup Timeb,c
2
10 MHz Max 250 350 Min Max 200 300 NA 0 125 0 125 -150 5TcPc NA 190 190 200 150 150 140 120 120 400 50 1000 100 120 1000 NA
Min
NA 0 150
NA
TsRXD(RXCr) RxD to RxC High Setup Time ThRXD(RxCr) RxD to RxC High Hold Time
TsRXD(RXCf) RxD to RxC Low Setup Time2,d 0 ThRXD(RXCf) RxD to RxC Low Hold Time TsSY(RXC) ThSY(RXC) TsTXC(PC) SYNC to RxC High Setup Time2
2,4
150 -200
SYNC to RxC High Hold Time2 5TcPc TxC Low to PCLK High Setup Timee,3 NA
TdTXCf(TXD) TxC Low to TxD Delay5 TdTxCr(TXD) TxC High to TxD Delay5,4 TdTXD(TRX) TwRTXh TwRTXI TcRTX TxRx (DPLL) TcRTXX TwTRXh TxD to TRxC Delay RTxC High Widthf TRxC Low Width
6
130 130 472
7,h
RTxC Cycle Time6,g DPLL Cycle Time Min Crystal Osc. Periodi TRxC High Width
6
59 118 130
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
81
Table 10. Z80C30 General Timinga (continued) 8 MHz No 19 20 21 22
a. b. c. d. e. f. g. h. i.
10 MHz Max Min 120 400 120 120 Max
Symbol TwTRXI TcTRX TwEXT TwSY
Parameter TRxC Low Width6 TRxC Cycle Time
6,7
Min 130 472 200 200
DCD or CTS Pulse Width SYNC Pulse Width
Units in nanoseconds (ns) otherwise noted. RxC is RTxC or (TRxC, whichever is supplying the receive clock. Synchronization of RxC to PCLK is eliminated in divide by four operation. Parameter applies only to FM encoding/decoding. TxC is TRxC or RTxC, whichever is supplying the transmit clock. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are identical to case PCLK requirements. The maximum receive or transmit data rate is 1/4 PCLK. Applies to DPLL clock source oniy Maximum data rate of 1/4 PCLK still applies DPLL clock should have a 50% duty cycle. Both RTxC and SYNC have 30 pf capacitors to ground connected to them.
Electrical Characteristics
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
82
PCLK 1 W/REQ Request 2 W/REQ Wait 3 RTxC, TRxC Receive 4 RxD 8 SYNC External 10 11 TxD 10 TRxC Output 14 RTxC 18 17 TRxC 18 20 CTS, DCD 21 SYNC Input 22 22 21 19 15 12 9 5 6 7
TRxC, RTxC Transmit
Figure 39. Z80C30 System Timing Diagram
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
83
Table 11. Z80C30 System Timing 8 MHz No 1 2 3 4 Symbol Parameter
,1,2,c
10 MHz Max 12 14 7 12 3 5 11 7 6 3 6 3 3 Min 8 8 4 81 2 8 5 4 4 2 2 2 2 11 7 6 3 6 3 3 Max 12 14 7 2 3
Min 8 8 4 8 2
e,2
TdRXC(REQ) RxC High to W/REQ Valida,b TdRXC(W) RxC High to Wait Inactive TdRdXC(SY) RxC High to SYNC Valid1,2 TdRXC(INT) RxC High to INT Valid Noted,2
1,2,3
5 6 7 8
TdTXC(REQ) TxC Low to W/REQ Valid TdTXC(W)
58 5 4 4 2 2 2 2
TxC Low to Wait Inactive1,2,3
2,3
TdTXC(DRQ) TxC Low to DTR/REQ Valid TdTXC(INT) TxC Low to INT Valid1,2, Note
2,4
9a 9b 10
a. b. c. d. e.
TdSY(INT) TdSY(INT) TdEXT(INT)
SYNC to INT Valid2,3 SYNC to INT Valid Note2,3,4
2,3,4
RxC is RTxC or TRxC whichever is supplying the receive clock. Units equal to TcPc. Open-drain output, measured with open-drain test load. Units equal to AS. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
Electrical Characteristics
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
84
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Electrical Characteristics
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
83
Packaging and Ordering
Package Information
Figures 40 and 41 illustrate the 40-pin DIP package and 44-pin PLCC package diagrams.
Figure 40. 40-Pin DIP Package Diagram
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Packaging and Ordering
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
84
Figure 41. 44-Pin PLCC Package Diagram
Ordering Information
Z80C30/Z85C30
Table 12 provides ordering information for the Z80C30 and the Z85C30 devices.
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Packaging and Ordering
Z80C30/Z85C30 CMOS SCC Serial Communications Controller
85
Table 12. Z80C30/Z85C30 Ordering Information 8 MHz Z80C3008PSC Z80C3008VSC Z85C3008PSC/PEC Z85C3008VSCNEC 10 MHz Z80C3010PSC Z80C3010VSC Z85C3010PSC/PEC Z85C3010VSCNEC 16 MHz Z85C3016PSC Z85C3016VSC
Package P = Plastic DIP V = Plastic Leaded Chip Carrier D = Ceramic DIP Temperature E = -40C to + 100C S = 0 to +70C Speeds 8 = 8 MHz 10 = 10 MHz 16 = 16 MHz Environmental C = Plastic Standard
Packaging and Ordering
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Z80C30/Z85C30 CMOS SCC Serial Communications Controller
86
Example:
Example Z 80C30 16 P S C
is a Z80C30, 16 MHz, PLCC, 0 C to +70 C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number ZiLOG Prefix
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Packaging and Ordering

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